1. Field of the Invention
Example embodiments of the present invention relate generally to a semiconductor memory device and methods thereof, and more particularly to dynamic random access memory (DRAM) devices and methods thereof.
2. Description of the Related Art
A typical dynamic memory cell may include one access transistor and one data storage capacitor. A first logic level (e.g., a higher logic level or logic “1”) may be stored if a sufficient or threshold charge is charged in the data storage capacitor, and a second logic level (e.g., a lower logic level or logic “0”) may be stored if there is not a sufficient charge in the data storage capacitor. However, over time, a charged capacitor may gradually lose its charge, such that a periodic refresh may be perform to maintain the capacitor in a “charged” state. If a memory cell array of a conventional semiconductor memory device includes dynamic memory cells with data storage capacitors, it may be difficult to reduce a layout size of the semiconductor memory device.
Accordingly, conventional semiconductor memory devices may include transistors having a floating body. Such a transistor may store a majority carrier and may need be refreshed periodically because the stored majority carrier may disappear after a given period of time. A memory cell including the “floating body” transistor may not include a capacitor (e.g., a data storage capacitor), but rather may operate as a “dynamic memory” cell because the floating body transistor may operate similar to a data storage capacitor. A layout size of semiconductor memory devices including floating body transistors may be relatively cell because, typically, a single floating body transistor is deployed within each dynamic memory cell.
Conventional semiconductor memory devices including dynamic memory cells, each including a single floating body transistor, may commonly apply a ground voltage to sources of a plurality of memory cells in the memory cell array. The sources of the memory cells may common, or shared, and as such may be arranged to cover an entire surface of a substrate of the semiconductor memory device. Conventional semiconductor memory devices may commonly apply the ground voltage to the sources of the memory cells of the memory cell array and may adjust a voltage applied to the bit line and/or the word line to perform a write or read operation.
FIG. 1 is a plane view illustrating a layout of a conventional dynamic random access memory (DRAM) cell array. FIGS. 2 and 3 are cross-sectional views taken along lines A-A′ and B-B′ respectively, of FIG. 1. The layout of the conventional DRAM cell array is described below with reference to FIGS. 1 to 3.
Referring to FIGS. 1 through 3, a pillar-type silicon layer 2 may be formed at a location of each memory cell MC, and each memory cell MC may include a vertical MOS transistor formed with the pillar-type silicon layer 2. The transistor of each memory cell MC may be formed such that a gate insulating layer 3 may surround the pillar-type silicon layer 2, and an n+-type source diffusion layer 6 may be formed below the pillar-type silicon layer 2. The source diffusion layer 6 may be formed above an entirety of the surface of a substrate 1 to electrically insulate a p-type region of the pillar-type silicon layer 2 from a p-type region of the substrate 1. Thus, in each memory cell MC, the pillar-type silicon layer 2 may be maintained in a “floating” state. The source diffusion layer 6 may be formed to cover the entirety of the surface of the substrate 1 and may bind the memory cells MC to a fixed potential line SS. A surface, which may form the transistor, may be converted by an interlayer insulator 7, and bit lines 8 may be formed on the interlayer insulator 7. The bit lines 8 may extend in a perpendicular direction to word lines to be connected to drain diffusion layers 5 of the memory cells MC. Thus, in summary, the source diffusion layer 6 may be formed so as to cover an entirety of the surface of the substrate 1, and the fixed potential lines SS may be commonly connected to the source diffusion layer 6.
FIG. 4 illustrates an equivalent circuit of the conventional DRAM of FIG. 1. Referring to FIG. 4, four memory cells MC having a floating body may be arranged between the word lines WLi and WLi+1 and the bit lines BLi and BLi+1. Drains of the memory cells MC may be respectively connected to the corresponding bit lines BLi and BLi+1, gates of the memory cells MC may be respectively connected to the corresponding word lines WLi and WLi+1, and sources of the memory cells MC may be connected to a common source line SL. While not shown in FIG. 4, the floating bodies of the memory cells MC may be respectively connected to corresponding drains.
Write and read operations of the conventional memory cells of FIG. 4 will now be described in greater detail.
In conventional write operation of the memory cells MC of FIG. 4, the memory cells MC may use an accumulation of a number of holes, which may be the majority carrier in the floating body of the NMOS transistor which may constitute the memory cell MC. For the write operation, a ground voltage may be applied to the common source line SL, a positive voltage of a first voltage level may be applied to the word line, and a positive voltage of a second voltage level may be applied to the bit line. A relatively large number of electron-hole pairs may be generated around the drain of the NMOS transistor by impact ionization. Of the electron-hole pairs, the electrons may be absorbed to the drain, and the holes may be stored in the floating body, such that the first logic level (e.g., a higher logic level or logic “1”) may be written. Alternatively, if a positive voltage of the first voltage level is applied to the word line and a negative voltage of a third voltage level is applied to the bit line, the floating body and the drain may be forward-biased, and a majority of the holes stored in the floating body may be discharged to the drain, such that the second logic level (e.g., a lower logic level or logic “0”) may be written. A threshold voltage of the NMOS transistor may be reduced if the first logic level is stored, whereas the threshold voltage of the NMOS transistor may be raised if the second logic level is stored. Thus, the threshold voltage of the NMOS transistor storing the first logic level (e.g., a higher logic level or logic “1”) may be lower than the threshold voltage of the NMOS transistor storing the second logic level (e.g., a lower logic level or logic “0”). Accordingly, data may be read based on the threshold voltage of the NMOS transistor during a read operation.
In conventional operation of the memory cells MC of FIG. 4, after the write operation, a negative voltage may be applied to the word line to maintain a state of the threshold voltage of the NMOS transistor storing the first logic level (e.g., a higher logic level or logic “1”). A read operation may thereafter be performed in the data maintaining state.
In conventional read operation of the memory cells MC of FIG. 4, a ground voltage may be applied to the common source line SL, and a voltage between a threshold voltage of the NMOS transistor corresponding to the first logic level and the second logic level may be applied to the word line. An electric current need not flow through the NMOS transistor storing the second logic level, but an electric current may flow through the NMOS transistor storing the first logic level. Thus, if the NMOS transistor stores a threshold voltage corresponding to the second logic level, there may be substantially no electric current change in the bit line connected to the NMOS transistor, and there may be at least some electric current adjustment occurring in the bit line connected to the NMOS transistor if the NMOS transistor is storing the first logic level. Thus, the first and second logic levels may be interpreted based upon a detection of whether or not an electric current fluctuation of the bit line.
As described above, conventional semiconductor memory devices may perform write and read operations by adjusting a level of the voltage applied to the word line and a level of the voltage applied to the bit line, to be set to the positive or negative level, while a ground voltage may be applied to the common source line SL.